VHDL descriptions generation for digital systems basing on Petri net model

Аuthors

Abstract

The features of mathematical modelling of up-to-date digital control and data processing systems are described in this paper. The requirements to the mathematical apparatus are stated and the necessity of provision of automated conversion the mathematical model of a digital system to the input format of the up-to-date synthesizing CAD. Some of original author’s constructions with VHDL language whish permit adequately represent mathematical models of digital systems, given with the help of strict — hierarchical synchronous Petri nets are considered. The obtained results provide possibility of organization of a through computer-assisted design of digital systems from a stage of mathematical modelling up to a stage of low level logic synthesis, that allows considerably reduce time of development, lower complexity and improve the design’s quality.